1. Technical Field
The present invention relates to a semiconductor apparatus, and more particularly, to a nonvolatile memory apparatus and a verification method thereof.
2. Related Art
A nonvolatile memory apparatus, or particularly, a flash memory apparatus not only may be applied to a computer, a memory card and so on, but also the application field thereof has been expanded to a portable information device such as a wireless communication terminal and a digital camera.
In the flash memory apparatus, the level of data stored in each memory cell is defined by the threshold voltage of the memory cell, and thus a program operation may be referred to as a process of changing the threshold voltage of a memory cell.
In the flash memory apparatus, the program operation is generally performed according to an ISPP (Incremental Step Pulse Program) method.
When it is assumed that all memory cells which are to be programmed have the same program speed, the threshold voltages of the programmed memory cells after the program operation will have the same distribution as before the program operation.
However, the memory cells cannot have the same program speed, due to a variety of reasons occurring during the manufacturing process of the memory apparatus and a change of external condition depending on the use of the memory apparatus. Therefore, the program operation is performed by a method of increasing a program pulse, that is, the ISPP method.
That is, a first-step program pulse is applied to program the selected memory cells. Then, a verification voltage is applied to the selected memory cells to pass memory cells having a higher threshold voltage than the verification voltage. After that, the program voltage is increased by a constant step to apply a second-step program pulse to the memory cells having a threshold voltage equal to or lower than the verification voltage, and the program operation is then performed. Such a process is performed until all the memory cells are completely programmed. The memory cells passed at the previous program step are prohibited from being programmed, in order to substantially prevent over-programming.
As such, since the memory cells programmed at high speed and the memory cells programmed at low speed are mixed during the program operation, the program operation can be completed only when the memory cells programmed at low speed are completely programmed. Therefore, the program time is determined by a memory cell of which the program speed is the lowest.
However, when the number of memory cells which are not completely programmed, that is, the number of memory cells which are processed as fail cells during a verification process corresponds to such a level that can be recovered by an error correction algorithm, the program operation does not need to be performed until all the memory cells are programmed.
Therefore, a fail bit sensing unit is used to count the number of memory cells processed as fail cells during the verification process. Furthermore, when the counting result of the fail bit sensing unit corresponds to such a level that may be corrected, an error correction circuit of a controller performs an error correction on the corresponding cells such that the program operation is completed.
The fail bit sensing unit may be configured by using a current sensing circuit (CSC), and the configuration thereof will be described with reference to FIG. 1.
FIG. 1 is a diagram illustrating a conventional fail bit sensing unit 150.
The fail bit sensing unit 150 includes a CSC which is configured to compare current values read from the selected memory cells of the memory cell array 110 with a reference current and output a pass or fail decision. Here, the reference current is decided in correspondence to a bit number which can be corrected by the ECC.
That is, the fail bit sensing unit 150 determines a pass or fail according to whether a variation in current amounts of page buffers is allowable or not, during the verification operation after the program operation. The current amounts of the page buffers are changed by the number of memory cells which are not completely programmed, that is, the number of fail bits.
However, the amounts of current flowing in memory cells may have deviations, depending on the physical properties of the memory cells. Furthermore, when the sum of such deviations is equal to or larger than a cell current amount for one cell, an error may occur in counting the number of fail bits. For example, it may be assumed that the cell current amounts of all the memory cells have a deviation of +10% in comparison with an intended cell current amount. In this case, when 10 fail bits are to be counted, a current corresponding to 11 bits may be measured due to the deviations in current amount.
FIG. 2 is a diagram explaining an accumulative error according to the number of fail bits.
Referring to FIG. 2, when the magnitude of current flowing in one memory cell is assumed to be five, a deviation in cell current amounts does not have an effect upon the precision of fail bit sensing, in case where the number of fail bits is equal to or less than four.
However, as the number of fail bits increases, an error of the total current amount sensed by the fail bit sensing unit 150 gradually increases.
Such a deviation in cell current amounts may have an effect upon the current sensing operation of the fail bit sensing unit 150. In this case, even when it should be determined that the number of fail bits corresponds to such a level that can be corrected by the ECC, a fail signal may be outputted, and even when the number of fail bits does not correspond to such a level that can be corrected by the ECC, a pass signal may be outputted.